In the design of a system-on-chip (SoC) there are several design methodologies, such as design for test (DFT), design for manufacturing (DFM), and design for debug (DFD), collectively known as DFX, for example, that can be used to increase the testability, fault coverage and manufacturing yield of the SoC. DFX may include design modifications that provide improved access to internal circuit elements such that the local internal state can be observed (observability) more easily. The design modifications can be strictly physical in nature (e.g., adding a physical probe point to a network or “net”) and/or may include adding active circuit elements to facilitate observability (e.g., inserting a multiplexer “mux” into a net).
For example, design modifications may be made to facilitate testing a single logic gate at a moment in time. However, most gates are deeply embedded whereas the test equipment is typically connected to the primary Input/outputs (I/Os) and/or some physical test points. The embedded gates, hence, must be manipulated through intervening layers of logic. If the intervening logic contains state elements, then the issue of an exponentially exploding state space and state transition sequencing causes difficulties for testing.